Field of the Invention
The present invention relates to bipolar transistors, in general, and more particularly, to a dual-dielectric emitter bipolar transistor utilizing direct tunneling of minority carriers as the primary mechanism of operation.
Prior Art Discussion
Basically, there exists, for the most part, two types of fabricated transistor structures, namely bipolar and field effect transistors. The fabrication of the bipolar transistor entails two diffusion or equivalent steps for incorporating the base and emitter regions into the collector region. The first step usually diffuses the base region into the collector region and the second step diffuses the emitter region into the already diffused base region. This second step is generally very sensitive and not well controlled especially when a uniform, narrow base width region is required, for example in microwave applications at frequencies in the GHz range. The more recently developed insulated gate field effect transistors (IGFET) require only one diffusion or equivalent step for fabrication thereof. A second process step is performed by the deposition of insulation layers in a selected region of the semiconductor surface and a metal gate contact is deposited on top of the insulation layers. The deposition steps are considered usually a well-controlled process which overcomes the problems associated with the sensitive diffusion step of the bipolar fabrication. However, the operational response times characteristic of IGFET's appear not to be as good as bipolar transistors for microwave applications.
Contrasting the operation of the two devices, the bipolar transistor is operative to inject minority carriers across the emitter-base junction into the base region when an appropriate forward bias voltage potential is applied across the emitter-base junction. The base region is usually lightly doped to allow for a good ratio of current injected into the base to current injected from the base into the emitter. A large percentage of these minority carriers transport across the base without recombination and cross the collector-base junction due to the energy from a reverse bias voltage potential applied across the base-collector junction. On the other hand, the IGFET's, such as metal-oxide-semiconductors (MOS) or metal-nitride-oxide-semiconductors (MNOS) do not inject carriers across the gate-insulator-semiconductor interface, but rather develop a space charge region on the surface of the semiconductor at the insulator-semiconductor interface. When an electric field is developed across the insulator(s) is of a correct polarity and sufficient magnitude, an inversion layer is produced in a channel between the source and drain regions of the device which enables the source to inject carriers through this space charge inversion layer channel to a drain which is biased in relation to the source to collect the injected carriers.
The fabrication process of the IGFET's is considered to be better controlled, requires one less diffusion step, and the gates or cells are self-isolating from other cells fabricated on same substrate. For these reasons, it has been generally chosen as the main cell structure used in most medium-scale (CMSI) and large-scale integration (LSI) circuits-on-a-chip. However, these IGFET's do have limitations involving response times and current drive capacity. Generally bipolar devices are used when high frequency response is required, such as for microwave applications for example, or when it is required to supply high output drive currents over relatively short time periods as in some microcomputer and high speed memory applications, and for these reasons attempts are sometimes made to fabricate both bipolar and IGFET's on the same substrate. This process becomes lengthy and complicated due to the second diffusion process step and cell structure isolation which are usually required for the fabrication of the bipolar devices. In addition a high quality gate oxide must be provided for the MOS transistors, in most cases. A desirable alternative is to have a transistor device having bipolar characteristics, yet being compatible with the IGFET fabrication process.
Recently, investigative research has been conducted on thin-oxide MNOS memory transistor for application in non-volatile charge storage memory devices wherein charge is stored in deep traps at or near the nitride-oxide interface. Charge transport in these devices takes place across the semiconductor-insulator interface. Several conduction mechanisms have been employed to explain this charge transport. In one analysis, with an oxide thickness in the range of 50-200A, the current transport was considered to be of Fowler-Nordhiem tunneling (indirect tunneling) in the oxide layer and Poole-Frenkel conduction in the nitride. In another examination of an MNOS structure having oxide thicknesses in the range of 15-35A, the current transport mechanism in the oxide was considered direct tunneling from deep traps in the insulator-insulator interface to the silicon energy conduction band. Reference is made to a paper published in the IEEE Transactions on Electron Devices, Vol. ED-19, No. 12 dated December, 1972 entitled "Characteristics of Thin-Oxide MNOS Memory Transistors" by White and Cricchi and also to a U.S. Patent No. 3,577,210; entitled "Solid State Storage Devices" by Hans G. Dill; patented May 4, 1971 for a more detailed understanding of the aforementioned insulator-semiconductor carrier injection mechanisms.
In the past, attempts have been made to utilize insulator-semiconductor junctions in transistor applications. Examples are found in the U.S. Pat. No. 3,060,327 issued to Dacey; patented Oct. 23, 1962 and the U.S. Patent No. 3,462,700 issued to Berglund et al; patented Aug. 19, 1969. The Dacey patent employs a p-n-p transistor structure wherein the p-n emitter-base junction is avalanched in response to a reverse bias voltage potential applied thereacross such that majority carriers are avalanched across the barrier of the junction into the n-type base region. In one embodiment of the Dacey invention, a dielectric insulator is fabricated adjacent to the n-type base region to form an n-p base-collector junction and when positively biased in relation to the base potential, the insulator region is used to collect the majority carriers through the emitter-base junction. Dacey's invention appears to operate as a hot electron carrier device wherein the majority carriers suffer many collisions in their transit through the n-type base to the insulation layer. For this reason, the base region must be fabricated very thin and dielectric must also be very thin in order for the majority carriers to maintain enough energy to overcome the potential barrier at the base collector junction. Devices employing the avalanche mechanism are known to generally exhibit electrical noise problems in their operation.
The Berglund et al patent appears to operate on the principle of a field effect device. In one embodiment of the Berglund et al invention, a p-type heavily doped (degenerate level doping) material is sandwiched between a dielectric film on an n-type bulk silicon material. Metal electrodes are adhered to each layer such to affect biasing across each of the two junctions -- insulator/p-type and p-type/n-type. The creation of minority carriers is affected within the p-type silicon material at the insulator surface caused principally by the bending of the energy bands according to the bias voltage potential applied across the insulator. A sufficient enough electric field applied across the insulator will produce an avalanche mechanism to occur in the p-type silicon such that carriers tunnel from the conduction band to the valence band of the heavily doped p-type material. It appears that no carriers are injected across the insulator-semiconductor junction with this operation. It further appears that Berglund's invention is limited in that it requires the use of a degenerately doped p-type base which is slightly more difficult to produce and further, since it employs the avalanche mechanism, it may also be electrically noisy in operation as devices employing avalanche mechanisms generally are.
It is evident from the above discussion that a transistor device having bipolar characteristics which are functionally well suited for high frequency application, say in the GHz range, and having a compatible fabrication technology with the MOS, MNOS and CMOS transistor structures would be of paramount importance to the solid-state industry. In addition, the elimination of the second processing step for fabricating bipolar transistors could accordingly bring about a reduction in required process control possibly rendering a savings in production cost and time. An improved control of transistor base width construction could yield high frequency response characteristics without special fabrication techniques over that which is presently available.